The inventive concept relates to the semiconductor device package technologies. In particular, the inventive concept relates to semiconductor device packages and to methods of fabricating the same.
With the rapid spread of electronic products such as mobile phones, tablet PCs and digital cameras, semiconductor device packages find themselves gaining in use. One example of a semiconductor device package is a Flip-Chip Ball Grid Array (FCBGA) semiconductor device package. Typical in such a package, an active surface of at least one semiconductor chip is electrically connected to one surface of a substrate via a plurality of conductive bumps. An underfill is provided between the semiconductor chip and the substrate so that the underfill encloses each of the conductive bumps and fills the spaces between the conductive bumps to protect the conductive bumps and support the semiconductor chip. Meanwhile, the other surface of the substrate is provided with a plurality of solder balls as input/output terminals of the package. Such design has become a mainstream packaging technology for electronic components nowadays, as it provides for a significantly compact package helping to meet industry demand for miniaturizing electronic products.
In this respect, semiconductor device packages have become thinner. Therefore, the diverse coefficients of thermal expansion (CTE) of various components in the semiconductor device package increase the likelihood that components will warp as the semiconductor device package is being fabricated. In the case that such warping of components occurs, an electronic connection between the substrate and the semiconductor device package or between the conductive bumps of the semiconductor chip and the substrate may fail. In addition, after soldering the conductive bumps to the substrate by a reflow process, warping induced by a shrinking of the substrate may also lead to cracking of the conductive bumps, which may impair the electrical connections and reduce the overall quality of the end product.
U.S. Published Patent Application No. 2015/0303158A1 discloses a semiconductor die package which can prevent warping and improve adhesion. As shown in FIG. 1, a conventional FCBGA semiconductor device package 12 includes a die 121, through package vias (TPVs) 122, molding compounds 123 and 128, a first redistribution structure 124, a second redistribution structure 125, solder balls 126 and connectors 127. The different CTEs between the components tend to cause upward warping at the edges of the semiconductor device package 12. As shown in FIG. 2, the semiconductor device package 12′ disclosed in the U.S. patent publication uses a material 212 which can supply compressive stress to form a second redistribution structure 125 in order to balance thermally induced forces generated in the semiconductor device package 12′. FIG. 3 is an enlarged view of a rectangular portion P in FIG. 2. As shown in FIG. 3, a compressive stress layer 212 is provided as a bottom layer of the stacked second redistribution structure 125, and is disposed on the molding compound 123 and the TPV 122 while exposing a portion of the TPV 122. The passivation layer 214 is provided above the compressive stress layer 212. The second redistribution wiring 213 is buried in the compressive stress layer 212 and the passivation layer 214.
However, although such a design can reduce warping in the semiconductor device package, the warping can only be mitigated to a limited extent by the compressive stress layer provided in the redistribution structure due to a limited thickness of the redistribution structure in the semiconductor device package, and defects related to the warping produced by epoxy molding compound (EMC) cannot be sufficiently controlled.